1. Field of the Invention
The present invention generally relates to changing the function of a control device. More particularly, the invention concerns an apparatus, method, and article of manufacture for upgrading the logical configuration of a field programmable gate array integral to a control device for a hardware element.
2. Description of the Related Art
In the manufacture of computers, it is a common practice to use a control device, or controller, to manage the operational characteristics of a hardware element. In turn, the controller commonly includes a programmable logic device ("PLD"). This arrangement allows the operational characteristics, or functions, of the controller to be updated as necessary. One example of this arrangement is using a field programmable gate array or "FPGA"--one type of PLD--to manage the operational characteristics of a direct access storage device controller for a direct-access storage disk ("DASD").
Typically, one part of the controller is a dedicated special-purpose microprocessor which controls the details of input and output ("I/O") data transfers to and from an I/O device. The microprocessor manages the details of the command and data transfer after a main processor initiates the transfer. Using a controller allows the main processor to proceed with execution of a program while the command or data transfer takes place.
Although a controller manages the data transfer for the I/O device, the method in which the data is transferred is limited to the original configuration of the controller. To overcome this limitation and allow the controller configuration to be changed without physically removing the controller, an FPGA is used in conjunction with the controller. The FPGA is a programmable device which stores its programming configuration in volatile random access memory cells. The memory cells are typically located within the FPGA. By changing the configuration of the FPGA, the operational characteristics of the controller can be altered. This occurs because the logic gates within the FPGA are reconfigured to allow the input commands or data sent to the controller to be managed differently than before.
To program an FPGA, a desired logical configuration is copied to the FPGA from a storage unit when the computer is started. Logical configuration refers to the actual configuration of the FPGA, and is accomplished by sending configuration data to the FPGA to establish the "personality" of the FPGA. The "personality" of the FPGA refers to the method by which the FPGA performs requested functions, or receives or outputs data or commands. In this regard, the sequence in which the FPGA handles commands or data may be altered by changing the programming, i.e. the configuration of the FPGA. Similarly, the timing and sequencing at which commands or data are sent may also be changed. By changing the way the FPGA handles commands and data, the operational characteristics of the controller can be modified.
Once configured, the FPGA receives data and/or commands from a processor in a host computer when a request is made from the host computer for an associated I/O device to perform an operation, such as retrieving stored data or locating a requested location on a disk. The FPGA then manages the transfer and any data or commands to the I/O device. The I/O device executes the request. This arrangement--using an FPGA to establish the operational characteristics of the controller--allows the functions performed by the controller to be altered without having to physically replace the controller or any of its components. By changing the controller's operational characteristics, the operation of the I/O device associated with the controller is altered.
Generally speaking, there are two instances where an FPGA is configured. As indicated above, the first instance is when an FPGA begins from a cold start. One example is a power-on reset after which the device is devoid of data; another example is where a power disturbance causes the FPGA's configuration to fail.
The second instance in which an FPGA is configured is during normal operation, when the power is on and the device already contains a specific configuration. In this case, the user may desire to change the FPGA to a different configuration.
In the quest to find faster methods for re-configuring an FPGA, several methods have evolved. One method is known as the "master serial mode." Here, the FPGA receives configuration data and commands from a special serial programmable read only memory, or "PROM," when the FPGA is otherwise disabled from receiving data or commands from a host computer. The PROM is specifically programmed with the configuration data for the FPGA. The contents of the PROM are customarily generated using development tools provided by the FPGA manufacturer or the manufacturer of the hardware device which the FPGA is being used to control. During the configuration operation, the FPGA reads in the PROM's contents bit-by-bit. In the master serial mode, the timing and control signals of the configuration operation are controlled by the FPGA. A major concern in using this arrangement is that one PROM is required for each FPGA. The overall component cost of the PROMs and the board real estate requirements can be considerable if multiple FPGAs are involved.
Another technique of configuring FPGAs is the "master parallel mode." As with the master serial mode immediately above, the FPGA controls the timing and control signals for the operation. The difference in the two methods is that the FPGA reads the configuration data from an 8-bit PROM one-byte at a time instead of one-bit at a time. Nevertheless, because the FPGA then serializes the data for internal utilization, this method of configuring the FPGA ultimately requires the same amount of time as the master serial mode. Unfortunately, the same cost and real estate requirements associated with the master serial mode still apply.
Another method is the "slave serial mode," so named because the FPGA does not control the configuration sequence. Instead, timing and control of signals during the configuration operation are performed by hardware devices external to the FPGA. For example, the configuration may be controlled by a host computer to which the FPGA is integrated, by a microprocessor, by an operator of the computer configuring the FPGA directly from a storage disk, or any similar method.
A major problem with each of the programming techniques discussed above is that the I/O hardware device that is being managed by the controller--a DASD in the case of a DASD controller--must be disabled from receiving input or sending output to the system during the FPGA reconfiguration process. Effectively, the I/O hardware device is operationally unavailable during the configuration process. In computers that are continuously in operation, the unavailability of the I/O hardware device can cause significant economic loss and inconvenience, even in computers using redundant hardware elements.